TMS320 Second-Generation Digital Signal Processors

* TMS320 Specification

• 80-ns Instruction Cycle Time

• 544 Words of On-Chip Data RAM

• 4K Words of On-Chip Secure Program EPROM (TMS320E25)

• 4K Words of On-Chip Program ROM (TMS320C25)

• 128K Words of Data/Program Space

• 32-Bit ALU/Accumulator

• 16 × 16-Bit Multiplier With a 32-Bit Product

• Block Moves for Data/Program Management

• Repeat Instructions for Efficient Use of Program Space

• Serial Port for Direct Codec Interface

• Synchronization Input for Synchronous Multiprocessor Configurations

• Wait States for Communication to Slow Off-Chip Memories/Peripherals

• On-Chip Timer for Control Operations

• Single 5-V Supply

• Packaging: 68-Pin PGA, PLCC, and CER-QUAD

• 68-to-28 Pin Conversion Adapter Socket for EPROM Programming

• Commercial and Military Versions Available

• NMOS Technology:

— TMS32020 . . . . . . . . . 200-ns cycle time

• CMOS Technology:

— TMS320C25 . . . . . . . . 100-ns cycle time

— TMS320E25 . . . . . . . . 100-ns cycle time

— TMS320C25-50 . . . . . . 80-ns cycle time

[Datasheet] TMS320.pdf (www.Alldatasheet.com)